1. Field of the Invention
The present invention relates generally to the field of analog-to-digital converters, and more specifically to such converters using sigma-delta (also known as delta-sigma) configurations.
2. Description of the Available Art
Converting analog signals to digital signals is accomplished using an analog-to-digital converter (ADC). An ADC circuit may contain a sigma-delta modulator circuit which is used to oversample an analog input signal. A decimation filter is required to follow the sigma-delta modulator circuit to filter and down-sample the digital output signal from the sigma-delta modulator to the Nyquist sample rate with minimal added in-band noise or distortion.
The standard topology for a sigma-delta A/D converter incorporates a low order analog-to-digital converter (ADC) to generate an output bitstream. This bitstream is sent both to a digital decimation filter to produce the final digital output, and to an input digital-to-analog converter (DAC) which, through a feedback loop, adjusts the subsequent output, based on the bitstream value.
The ADC is often implemented with a single comparator, taking the analog input and producing a single-bit digital output. This allows for a simple implementation of both A/D and D/A blocks. This approach becomes more difficult when designing a high order modulator because it is difficult to guarantee stability. This is due in part to overloading a single-bit comparator. As the input signal increases, the loop gain begins to drop rapidly and the system becomes unstable.
In order to avoid the instability associated with high order loops, multi-bit A/D and D/A architectures are normally used. This reduces the stability concerns associated with higher order loops because a system can be made with enough quantization levels such that overload will not occur and there is a graceful performance degradation as the modulator reaches saturation. Unfortunately this typically comes at the expense of a much more complex design, since it is difficult to achieve high linearity and low distortion from a simple multi-bit ADC. In contrast, a single bit ADC is linear by definition, eliminating much of the design effort of a multi-bit approach.
The linearity of an overall A/D conversion is no greater than the linearity of the internal blocks, namely the DAC and ADC. This is not a concern with a one-bit approach as these blocks are inherently linear. In order to stabilize higher order loops, several quantization levels may be required in these internal blocks. This requires a high level of control of the step size in the quantizer, as well as precise matching of components in the DAC which converts the digital output of the quantizer to an analog level added to the system input. Standard, inexpensive CMOS processes do not provide a ready solution to this problem as component matching capabilities are insufficient to achieve the desired linearity.
One available approach to this challenge has been to devise complex architectures to improve linearity beyond what is achievable with conventional design. This usually comes at the expense of more hardware on the integrated circuit.
There are several texts which generally describe sigma-delta data converters and refer to one-bit and multi-bit configurations of such converters. One such text is entitled: "Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation" by J. C. Candy and G. C. Temes, published by IEEE, January, 1992. Another such text is entitled: "Delta-Sigma Converters: Theory, Design and Simulation" by S. R. Norsworthy, R. Schreier and G. C. Temes, published by IEEE, November, 1996. Still another relevant text is entitled: "Analog-to-Digital and Digital-to-Analog Conversion Techniques" by D. F. Hoeschele, Jr., published by John Wiley & Sons, April, 1994 (Second Edition). The relevant content of these prior art publications is within the scope of information available to those having ordinary skill in the pertinent art and is hereby incorporated herein by reference as if fully set forth herein.